1. Field of the Invention
The present invention relates to a redundancy fuse read circuit for a semiconductor memory device, and more particularly, to an improved redundancy fuse read circuit that decreases chip size, power consumption and stress on the fuse without affecting its response time.
2. Discussion of the Related Art
As shown in FIG. 1, a redundancy fuse read circuit according to a first example of the related art includes an external voltage source detector 1, a gate control unit 2, a fuse FS10, a PMOS transistor PM11, an NMOS transistor NM11, and a latch 3.
The external voltage source detector 1 receives an external source voltage Vcc and a ground voltage Vss, and outputs a power up signal PWRUP. The gate control unit 2 receives the power up signal PWRUP, and outputs control signals FENB, FPR. The fuse FS10 has one terminal connected to source voltage Vcc. The PMOS transistor PM11 has its gate connected to a first control signal FENB and its source connected to another terminal of the fuse FS10. The NMOS transistor NM11 has its gate connected to a second control signal FPR, its drain connected to the drain of the PMOS transistor PM11, and its source connected to the ground voltage Vss. The latch 3 has its input terminal connected to a node N10, which is coupled in common to the drain of the PMOS transistor PM11 and the drain of the NMOS transistor, so as to latch the voltage at the node N10.
The latch 3 includes an inverter INV10 for inverting the voltage of the node N10 to output an output signal OUT; a PMOS transistor PM12 that has its source connected to the external source voltage Vcc, its gate connected to an output of the inverter INV10, and its drain connected to the node N10; and an NMOS transistor NM12 that has its drain connected to the node N10, its source connected to the ground voltage Vss, and its gate connected to the output OUT of the inverter INV10.
The operation of the redundancy fuse read circuit according to the first example of the related art will now be described.
First, when the external supply voltage Vcc transitions from LOW to HIGH, the external source voltage detector 1 generates the power up signal PWRUP, which is enabled at LOW. In the gate control unit 2, the control signals FENB, FPR are generated in accordance with the input of the power up signal PWRUP.
Here, the first control signal FENB denotes a signal enabled at LOW. When the power up signal PWRUP is disabled, it is switched to HIGH for turning off the PMOS transistor PM11. When the power up signal PWRUP is enabled, the first control signal FENB is enabled at LOW to turn on the PMOS transistor PM11.
The second control signal FPR is a signal that is enabled at a LOW, and when the power up signal PWRUP is disabled, it is turned to HIGH to thereby turn on the NMOS transistor NM11, so that the node N10 becomes reset to LOW. Also, when the power up signal PWRUP is enabled, the second control signal FPR is enabled to turn off the NMOS transistor NM11.
Therefore, when the fuse FS10 is open, the node N10, which is an output of a programmable fuse ROM, including the PMOS transistor PM11 and the NMOS transistor NM11 that are connected in series between the external source voltage Vcc and ground voltage Vss, is at LOW. When the fuse FS10 is closed, the node N10 is at HIGH. At this time, the latch 3 receives the voltage at the node N10 to be latched. Although the first control signal FENB is disabled to HIGH, the voltage at the node N10 is still stored in a memory.
As shown in FIG. 2, the redundancy fuse read circuit according to a second example of the related art includes a capacitor C20 having one terminal connected to the external source voltage Vdd and another terminal connected to a node N20, a fuse FS20 having one terminal connected to the node N20 and another terminal connected to the ground voltage Vss, a resistor R20 having one terminal connected to the external source voltage Vdd and another terminal connected to the node N20, a first PMOS transistor PM21 having a source connected to the external source voltage Vdd and a drain connected to the node N20, and a second PMOS transistor PM22 and an NMOS transistor NM20 connected in series between the external source voltage Vdd and the ground voltage Vss with their gates connected in common to the node N20 to output an output signal OUT, and having their drains connected in common to the gate of the first PMOS transistor PM21.
The operation of the redundancy fuse read circuit according to the second example of the related art will now be explained.
The fuse FS20 connected in series with the resistor R20 between the external source voltage Vdd and the ground voltage Vss is part of a main voltage branch which includes a fuse ROM. When the fuse FS20 is open, the voltage at the node N20 is at HIGH, and when the fuse FS20 is closed, the voltage at the node N20 is at LOW.
The inverter INV includes the second PMOS transistor PM22 and the NMOS transistor NM20, which are connected in series between the external source voltage Vdd and the ground voltage Vss. The latch LAT includes the inverter INV and a feedback circuit having the first PMOS transistor PM21, so that the inverter INV and the latch LAT can latch the voltage at the node N20.
Here, the capacitor C20 between the external source voltage Vdd and the node N20 sets a logic state of the node N20 using a capacitive coupling, when the external voltage Vdd changes abruptly.
As illustrated in FIG. 3, the redundancy fuse read circuit according to a third example of the related art includes an NMOS transistor NM30 and a floating gate transistor FGT, which are connected in series between the external source voltage Vdd and the ground voltage Vss, with their gates connected to a control signal PW and a predetermined voltage VL, respectively; a first inverter INV31 having its input terminal connected to the node N30 (which is connected in common to drains of the NMOS transistor NM30 and the floating gate transistor FGT); a PMOS transistor PM30 having its source connected to the external source voltage Vdd, its drain connected to the node N30 and its gate connected to the output of the first inverter INV31; a second inverter INV32 having an input connected to the output of the first inverter INV31; and an exclusive OR gate XOR30 having one input terminal connected to an output of the second inverter INV32 and another input terminal connected to an external address ADD.
The operation of the redundancy fuse read circuit according to the third example of the related art will now be explained.
The NMOS transistor NM30 and the floating gate transistor FGT, which functions as a fuse, are connected in series between the external supply voltage Vdd and the ground voltage Vss. A control signal PW is applied to the gate of the NMOS transistor NM30. A voltage VL is applied to the control gate of the floating gate transistor FGT to form a main branch of a fuse ROM 31.
The floating gate transistor FGT as a fuse has a high threshold voltage Vth when programmed, and a low threshold voltage when unprogrammed, so that an open or closed characteristic is obtained when the voltage VL is applied to the control gate of the floating gate transistor FGT. Therefore, the node N30 is HIGH or LOW depending on the voltage VL and on whether the floating gate transistor FGT is programmed or unprogrammed. Then, a voltage at the node N30 is latched in the latch 32, where a feedback loop is formed by the first inverter INV31 and the PMOS transistor PM30.
Meanwhile, when the external source voltage Vdd transitions and is set to a predetermined voltage, the control signal PW applied to the gate of the NMOS transistor NM30 of the fuse ROM 31 maintains HIGH during a short pulse, then the NMOS transistor NM30 is temporarily turned on to set the node N30 to HIGH. The HIGH signal at the node N30 is latched in a latch 32. Hence, even if the control signal PW is disabled, the HIGH at the node N30 is stored.
As shown in FIG. 4, the redundancy fuse read circuit according to a fourth example of the related art includes an NMOS transistor NM41 for applying a raised voltage Vpp to a fuse drain line; an NMOS transistor NM42 for applying an external source voltage Vcc to a redundancy row line; and fuse cells 41, 42 including an EEPROM (Electrically Erasable Programmable Read Only Memory) connected to the redundancy row line, the fuse drain line and the fuse gate line and receiving an external address signal ADD and inverted address signal /ADD for comparison.
The first fuse cell 41 includes NMOS transistors NM43, NM44, NM45 with their gates connected to the address signal ADD, and their drains connected to the fuse gate line, the redundancy row line, and the fuse drain line, respectively. The first fuse cell 41 also includes floating gate transistors FGT41, FGT42 with drains connected to the respective sources of the NMOS transistors NM44, NM45, and their sources connected to the ground voltage Vss. The second fuse cell 42 is identical to the first fuse cell 41 in structure although the inverted address signal/ADD, instead of the external address signal ADD, is applied to the second fuse cell 42.
The operation of the redundancy fuse read circuit according to the fourth example of the related art will now be explained.
The fourth example according to the related art employs an address matching in which the external address signal ADD and the inverted address signal /ADD are applied to the fuse cells 41, 42, respectively.
The floating gate transistors FGT41, FGT42 of the first fuse EEPROM cell and the second fuse EEPROM cell are connected in common, so that the raised voltage Vpp is applied to the fuse drain line. Through a program path passing from the fuse drain line through the NMOS transistor NM45 to the second floating gate transistor FGT42, the floating gate transistor FGT42 of the second fuse EEPROM cell is programmed to raise the threshold voltage Vth of the floating gate transistor FGT42, thereby raising the threshold voltage Vth of the first floating gate transistor FGT41 as well.
When the fuse information is read, the external source voltage Vcc is applied to the redundancy row line by the NMOS transistor NM42, and the read path goes from the redundancy row line to the NMOS transistor NM44 and from the NMOS transistor NM44 to the first fuse FGT41. At this time, the NMOS transistor NM43 allows a predetermined voltage to be applied to the fuse gate line to determine whether the floating gate transistors FGT41, FGT42 of the fuse EEPROM cell are turned on or off. Also, it is determined whether to pass or protect the predetermined voltage at the fuse gate line in accordance with the logic level of the address signal ADD by the floating gate transistors FGT41, FGT42.
As shown in FIG. 5, the redundancy fuse read circuit according to a fifth example, of the related art includes a fuse FS50 having one terminal connected to an external source voltage Vcc and another terminal connected to a second node N52; a first NMOS transistor NM51 having its drain connected to a second node N52, its source connected to the source voltage Vss and its gate connected to the first node N51; a capacitor C50 having one terminal connected to an external source voltage Vcc and another terminal connected to the first node N51; a second NMOS transistor NM52 having its drain connected to the first node N51, its source connected to the ground voltage Vss, and its gate connected to the second node N52; and a PMOS transistor PM50 having its source connected to an external source voltage Vcc, its drain connected to the first node N51 and its gate connected to the second node N52.
The operation of the redundancy fuse read circuit according to the fifth example of the related art will now be described.
In accordance with the opening or closing of the fuse FS50, the external source voltage Vcc rises, and the information at the fuse FS50 is read while being set to a predetermined voltage. In other words, when the fuse FS50 is open and the external source voltage Vcc rises, the capacitor C50 and a load capacitor at the first node N51 are set to HIGH by capacitive coupling. At this time, the voltage at the first node N51 is applied to the gate of the NMOS transistor NM51 to turn it on, and the second node N52 is connected to the ground voltage Vss. Therefore, the voltage at the second node N52 is applied to the gate of the PMOS transistor PM50 to turn it on, and a positive feedback sets the first node N51 to the external source voltage Vcc to latch the fuse information.
The redundancy fuse read circuit according to the first example of the related art has the following disadvantages. First, since the area occupied by the gate control unit 2 generating the control signals FENB, FPR is quite large, the size of the redundancy fuse read circuit is large. Also, because the fuse information latched in the latch 3 may be incorrect in accordance with the length the LOW interval of the first control signal FENB, the fuse information may be dominated by the first control signal FENB.
In the second example of the related art redundancy fuse read circuit, when the fuse FS20 is closed, a direct current path of the external source voltage Vdd and the ground voltage Vss is formed, thereby increasing power consumption. Also, the capacitor C20 between the external source voltage Vdd and the node N20 is effective only when the external source voltage Vdd abruptly changes, thus decreasing noise immunity. However, when the source voltage rise time is long, a bias setting function of the node N20 is lost. This is because the charge collected at the node N20 by the capacitive coupling is released through a leakage path.
In the third example of the related art redundancy fuse read circuit, an increase in the external voltage Vdd causes the voltage VL and the control signal PW to be concurrently generated. Accordingly, the third example is dominated by the length of the HIGH interval of the control signal PW, as the length of the LOW interval of the control signal FENB dominated the first example. Also, when the fuse is closed, a direct current flows between the external source voltage Vdd and the ground voltage Vss during the HIGH interval of the control signal PW, thereby increasing power consumption.
In the fourth example of the related art redundancy fuse read circuit, whenever an address signal transitions in the first fuse cell 41 for receiving the address signal ADD and in the second fuse cell 42 for receiving the inverted address signal /ADD, one of the two is always enabled so that a redundancy row line is connected to the first fuse drain and the fuse gate line is connected to the control gate. Therefore, more stress is applied to the fuse read circuit than to a given cell of a main cell array in a memory, so that the write time of a memory chip depends more upon the redundancy fuse longevity than on the cell of the main cell array. Also, when an address is set and a certain voltage is applied to the control gate and drain of the first fuse of the fuse cell, if the fuse is closed, a direct current path is formed between the external source voltage Vcc and the ground voltage Vss, thereby increasing power consumption.
With regard to the fifth example of the related art redundancy fuse read circuit, the capacitor C50 is connected between the external source voltage Vcc and the first node N51. When, the external source voltage Vcc is powered on, the capacitive coupling provided by the capacitor C50 and the load capacitor of the first node N51 is employed to set an initial bias of the first node N51, and the information of the fuse FS50 is latched by a gate input of the NMOS transistor NM51. If the rise time of the external source voltage Vcc during power-on is not limited, the drain junction leakage current of the PMOS transistor PM50 at the first node N51, the drain junction leakage current of the NMOS transistor NM52 and the large leakage current of the NMOS transistor NM51 do not allow the node initial bias to be set, whereby incorrect fuse information may be transferred through the inverter INV50.